HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES | ||||
JES. Journal of Engineering Sciences | ||||
Article 13, Volume 34, No 4, July and August 2006, Page 1283-1292 PDF (87.7 K) | ||||
Document Type: Research Paper | ||||
DOI: 10.21608/jesaun.2006.110784 | ||||
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Authors | ||||
M. Taher ![]() | ||||
1Electronic Engineer in Tibben Institute for Metallurgical Studies | ||||
2Faculty of Engineering, Helwan University, Cairo, Egypt | ||||
Abstract | ||||
In this paper, single-precision floating-point IEEE-754 standard Adder/Subtractor and Multiplier modules with high speed and area efficient are presented. These modules are designed, simulated, synthesized, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of normalization unit at the singleprecision floating-point multiplier and adder/Subtractor modules on the area, and speed is explained. | ||||
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