FPGA Implementation of Reconfigurable Parameters AES Algorithm
Rohiem, A., Ahmed, F., Mustafa, A. (2009). FPGA Implementation of Reconfigurable Parameters AES Algorithm. EKB Journal Management System, 13(AEROSPACE SCIENCES & AVIATION TECHNOLOGY, ASAT- 13, May 26 – 28, 2009), 1-9. doi: 10.21608/asat.2009.23495
A. E. Rohiem; F. M. Ahmed; A. M. Mustafa. "FPGA Implementation of Reconfigurable Parameters AES Algorithm". EKB Journal Management System, 13, AEROSPACE SCIENCES & AVIATION TECHNOLOGY, ASAT- 13, May 26 – 28, 2009, 2009, 1-9. doi: 10.21608/asat.2009.23495
Rohiem, A., Ahmed, F., Mustafa, A. (2009). 'FPGA Implementation of Reconfigurable Parameters AES Algorithm', EKB Journal Management System, 13(AEROSPACE SCIENCES & AVIATION TECHNOLOGY, ASAT- 13, May 26 – 28, 2009), pp. 1-9. doi: 10.21608/asat.2009.23495
Rohiem, A., Ahmed, F., Mustafa, A. FPGA Implementation of Reconfigurable Parameters AES Algorithm. EKB Journal Management System, 2009; 13(AEROSPACE SCIENCES & AVIATION TECHNOLOGY, ASAT- 13, May 26 – 28, 2009): 1-9. doi: 10.21608/asat.2009.23495

FPGA Implementation of Reconfigurable Parameters AES Algorithm

International Conference on Aerospace Sciences and Aviation Technology
Article 19, Volume 13, AEROSPACE SCIENCES & AVIATION TECHNOLOGY, ASAT- 13, May 26 – 28, 2009, May 2009, Page 1-9  XML PDF (426.55 K)
Document Type: Original Article
DOI: 10.21608/asat.2009.23495
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Authors
A. E. Rohiem; F. M. Ahmed; A. M. Mustafa
Egyptian Armed Forces.
Abstract
In this paper, a novel method of using customized (AES) variable parameters is introduced. This method depends on a continuous parameters reconfiguration and a customization of each internal block. The customization depends on varying the four transformations (polynomial and affine transformations for S-Box (SB), ShiftRows (SR) transformation, and MixColumn (MC) transformation). Internal AES blocks (SB, SR, and MC) are varied each round. Further more, these blocks are randomly interconnected during each session. The ciphered output was tested using avalanche, strict avalanche, and other NIST tests. This method overcomes (ECB) mode problems which appear when there is high redundancy in the plain data and also increasing strength against brute force attacks. The proposed AES is implemented on Field programmable Gate Arrays (FPGAs).
Keywords
Advanced Encryption Standard (AES); Electronic CodeBook (ECB); Field Programmable Gate Array (FPGA); National Institute of Standards and Technology (NIST)
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