RISC-V Core FPGA/ASIC Performance Comparison: A 45nm Case Study | ||
| The International Undergraduate Research Conference | ||
| Volume 6, Issue 6, September 2022, Pages 1-3 PDF (569.7 K) | ||
| Document Type: Original Article | ||
| DOI: 10.21608/iugrc.2022.302717 | ||
| Author | ||
| Mohammed El-desouky | ||
| Nanotechnology and Nano electronics Engineering Department , UST at Zewail City 12578 Ahmed Zewail Street, October Gardens 6th of October City, Giza, Egypt. | ||
| Abstract | ||
| RISC-V is an open Instruction Set Architecture (ISA) that is expected to dominate the market in the next few years. It is forecasted that market will consume 62.4 billion RISC-V CPU cores by 2025. In this project a RISC-V core is physically implemented as an ASIC using Nangate Open Cell Library 45nm PDK and its performance is compared to a 45nm based Spartan 6 FPGA implementation. | ||
| Keywords | ||
| FPGA; ASIC; RISC-V | ||
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