High Speed 1-tap Decision Feedback Equalizer in 28 nm CMOS | ||
| The International Conference on Electrical Engineering | ||
| Article 67, Volume 9, 9th International Conference on Electrical Engineering ICEENG 2014, May 2014, Pages 1-12 PDF (451.79 K) | ||
| Document Type: Original Article | ||
| DOI: 10.21608/iceeng.2014.30495 | ||
| Authors | ||
| Mostafa Hosny; Sameh Ibrahim; DiaaEldin Khalil; Mohamed Dessouky | ||
| EEC Department, Ain Shams University. | ||
| Abstract | ||
| Decision Feedback Equalizers (DFEs) are widely used in high speed serial links. DFE can compensate for severe distortion in transmitted signal due to band-limited channels. In this paper we demonstrate two different 1-tap DFE designs in 28 nm CMOS process with one reaching 66Gbps and the other reaching 83Gbps consuming 25mW and 32mW from a 0.9-V supply, respectively. No coils were used for bandwidth extension in the design. | ||
| Keywords | ||
| Decision Feedback Equalizer; high-speed equalizers; half-rate DFE | ||
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