Zero skew clock routing for fast clock tree generation
Reaz, M., Ibrahimy, M., Mohd-Yasin, F., Mohammad, A. (2008). Zero skew clock routing for fast clock tree generation. EKB Journal Management System, 6(6th International Conference on Electrical Engineering ICEENG 2008), 1-11. doi: 10.21608/iceeng.2008.34322
M. B. I. Reaz; M. I. Ibrahimy; F. Mohd-Yasin; A. Mohammad. "Zero skew clock routing for fast clock tree generation". EKB Journal Management System, 6, 6th International Conference on Electrical Engineering ICEENG 2008, 2008, 1-11. doi: 10.21608/iceeng.2008.34322
Reaz, M., Ibrahimy, M., Mohd-Yasin, F., Mohammad, A. (2008). 'Zero skew clock routing for fast clock tree generation', EKB Journal Management System, 6(6th International Conference on Electrical Engineering ICEENG 2008), pp. 1-11. doi: 10.21608/iceeng.2008.34322
Reaz, M., Ibrahimy, M., Mohd-Yasin, F., Mohammad, A. Zero skew clock routing for fast clock tree generation. EKB Journal Management System, 2008; 6(6th International Conference on Electrical Engineering ICEENG 2008): 1-11. doi: 10.21608/iceeng.2008.34322

Zero skew clock routing for fast clock tree generation

The International Conference on Electrical Engineering
Article 79, Volume 6, 6th International Conference on Electrical Engineering ICEENG 2008, May 2008, Page 1-11  XML PDF (125.87 K)
Document Type: Original Article
DOI: 10.21608/iceeng.2008.34322
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Authors
M. B. I. Reaz1; M. I. Ibrahimy1; F. Mohd-Yasin2; A. Mohammad2
1International Islamic University Malaysia, Kuala Lumpur, Malaysia.
2Multimedia University, Cyberjaya, Malaysia.
Abstract
Abstract:
A Zero Skew Clock Routing Methodology has been developed to help design team
speed up their clock tree generation process. The methodology works by breaking up
the clock net into smaller partitions, then inserting clock buffers to drive each portion,
and lastly, routing the connection from original clock source to each newly inserted
clock buffers with zero skew. A few Perl scripts and a new Visual Basic based routing
tool have been developed to support the methodology implementation. The routing
algorithm used in this tool is based on the Exact Zero Skew Routing Algorithm. The
methodology has been tested using a real design database and resulting in a significant
improvement in the through put time required to complete the clock tree generation.
This improvement is attributed to the ability to generate clock tree on much smaller
portions of clock nets that supports of speeding up the clock tree generation process in
IC design.
Keywords
Zero skew; Clock routing; Clock tree generation; IC design
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