Comparative Analysis of On-Chip FPGA Memory Architectures for Viterbi Decoder Implementation in DVB Systems | ||||
| JES. Journal of Engineering Sciences | ||||
| Article 3, Volume 53, Issue 4, July and August 2025, Page 136-154 PDF (978.91 K) | ||||
| Document Type: Research Paper | ||||
| DOI: 10.21608/jesaun.2025.344883.1393 | ||||
 View on SCiNiTO | ||||
| Authors | ||||
Asmaa Mosbeh1; Ali Younis1; Hassan Mostafa2; Khalil Yousef   1
| ||||
| 1Electrical Engineering Dept., Faculty of Engineering, Assiut University, Assiut, Egypt | ||||
| 2Electrical Engineering Dept., University of Waterloo, Canada | ||||
| Abstract | ||||
| High-definition Digital Video Broadcasting (DVB) systems demand high data rates, resulting in increased hardware complexity and power consumption, with the Viterbi decoder (VD) being a key contributor. The substantial memory resources required for these high data rates drive this research, which investigates the impact of diverse static random-access memory (SRAM) architectures on Zynq FPGA and their embedded memory resources, aiming to design power-efficient and less complex Viterbi decoders. Besides, the effect of different memories architectures on the transceiver (Tx-Rx) system has been studied. Viterbi decoder is implemented with different memory architectures on xczu7ev-2ffvc1156: flip flops, distributed RAM, block ram (BRAM), and UltraRAMTM (URAM). BRAM IP from AMD has significantly improved the dynamic power of Viterbi decoder by 97% compared to other available memories. Effectiveness of the employed BRAM is ensured by saving about 50% of the total power of the baseband transceiver system. That Tx-Rx operates at a frequency of 125MHz with a throughput of 62.3 Mbps, a code rate: ½, and 16APSK modulation scheme. Viterbi decoder has achieved a reduction in power compared to sleepy keeper and space time trellis code (STTC) with about 44% and 61% respectively. Functionality of the proposed VD architecture for signal to noise ratio (SNR) of 0 dB at additive white Gaussian noise (AWGN) channel and vector length of 3,264 bits is verified. Hardware validation on ZCU104 based on DVB standard is also done and reported. | ||||
| Keywords | ||||
| BRAM; URAM; LUTRAM. DVB; FPGA; Viterbi Decoder | ||||
| References | ||||
|
[1] P. Garcia, D. Bhowmik, R. Stewart, G. Michaelson, and A. Wallace, "Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing", Journal of Imaging, vol. 5, no. 1, 2019.
[2] Digital Video Broadcasting (DVB); framing structure, channel coding and modulation for digital terrestrial television, ETSI EN 300 744, January 2009.
[3] P. J. Black and T. H. Meng, "A 140-Mb/s, 32-state, radix-4 Viterbi decoder," in IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1877-1885, Dec. 1992.
[4] M. Véstias, H. Neto and H. Sarmento, "Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs," 2012 15th Euromicro Conference on Digital System Design, Cesme, Turkey, 2012, pp. 938-945.
[5] C. -J. Chen, C. Yu, M. -H. Yen, P. -A. Hsiung and S. -J. Chen, "Design of a low power viterbi decoder for wireless communication applications," IEEE International Symposium on Consumer Electronics (ISCE 2010), Braunschweig, Germany, 2010, pp. 1-4.
[6] R. Bhattacharjya et al., "Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders," Proceedings of the Great Lakes Symposium on VLSI 2023, TN, Knoxville, USA, 2023, pp. 409-413.
[7] AMD, " UltraScale Architecture Configurable Logic Block," UG574 (v1.5) [online], September 24, 2021. Available: https://docs.amd.com/r/en-US/ug574-ultrascale-clb
[8] AMD, " UltraScale Architecture Memory Resources User Guide," UG573 (v1.13) [online], September 24, 2021. Available: https://docs.amd.com/v/u/en-US/ug573-ultrascale-memory-resources.
[9] AMD, "ZCU104 Evaluation Board User Guide," UG1267 (v1.1) [online], October 9, 2018. Available: https://docs.amd.com/v/u/en-US/ug1267-zcu104-eval-bd.
[10] AMD, "Device Reliability Report," UG116 (v10.18) [online], June 25, 2024. Available: https://docs.amd.com/r/en-US/ug116.
[11] J. Jin and C. Y. Tsui, “Low-power limited-search parallel state Viterbi decoder implementation based on scarce state transition,” IEEE Transaction on Very Large-Scale Integration (VLSI) System, Vol. 15, no. 10, October 2007.
[12] Kalavathi Devi, T., Priyanka, E.B., Sakthivel, P. et al., "Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability," Analog Integr Circ Sig Process, vol. 109, no. 3 , pp. 487-499, 2021.
[13] M. J. Flynn, "Area - time - power and design effort: the basic tradeoffs in application specific systems," 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), Samos, Greece, 2005, pp. 3-6.
[14] A. Mosbeh, A. A. Y. Ibraheem, H. Mostafa, and K. Yousef, "Low Power Microarchitecture Designs of ACS Block in Viterbi Decoder: A Review", in Proceedings of the 2023 13th International Conference on Information Communication and Management, Cairo, Egypt, 2024, pp. 16–20.
[15] L. M. G. Rocha et al., "Physical implementation of an ASIC-oriented SRAM-based viterbi decoder," 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, Georgia, 2017, pp. 526-529.
[16] N. Prasad, I. Chakrabarti and S. Chattopadhyay, "An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3543-3554, Oct. 2018.
[17] C. Yu, Chien-Hung Kuo, Chen-Hen Sung, Mao-Hsu Yen and Sao-Jie Chen, "Design of a low-power OFDM baseband receiver for wireless communications," 2012 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, 2012, pp. 548-549.
[18] K. Cholan, "Design and Implementation of Low Power High Speed Viterbi Decoder", Procedia Engineering, vol. 30, pp. 61–68, 2012.
[19] Varada, S., Katpally, S. & Thiruveedhi, S.S.L. "Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles," J Electron Test, vol.36, pp. 343–363, 2020.
[20] D. A. F. Ei-Dib and M. I. Elmasry, "Low-power register-exchange Viterbi decoder for high-speed wireless communications," 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Phoenix-Scottsdale, AZ, USA, 2002, pp. V-V.
[21] R. Liu and K. K. Parhi, "Low-Latency Low-Complexity Architectures for Viterbi Decoders," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 10, pp. 2315-2324, Oct. 2009.
[22] R. A. Rashid, H. Harun, Z. Mansor, N. Shamsudin and S. M. Nor, "Pruning the algorithm complexity of the Add-Compare Select Unit (ACSU) for the Viterbi Decoder - A Review," 2018 IEEE 5th International Conference on Smart Instrumentation, Measurement and Application (ICSIMA), Songkhla, Thailand, 2018, pp. 1-5.
[23] M. Irfan, Z. Ullah, M. H. Chowdhury and R. C. C. Cheung, "RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs," in IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 28, no. 8, pp. 1925-1929, Aug. 2020, doi: 10.1109/TVLSI.2020.2993168.
[24] P. Musil, R. Juránek, M. Musil and P. Zemčík, "Cascaded Stripe Memory Engines for Multi-Scale Object Detection in FPGA," in IEEE Transactions on Circuits and Systems for Video Technology, vol. 30, no. 1, pp. 267-280, Jan. 2020, doi: 10.1109/TCSVT.2018.2886476.
[25] Tessier, R., et al, "Power-aware RAM mapping for FPGA embedded memory blocks," in Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006, pp. 189–198.
[26] R. Tessier, V. Betz, D. Neto, A. Egier and T. Gopalsamy, "Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 278-290, Feb. 2007, doi: 10.1109/TCAD.2006.887924.
[27] AMD, " Vivado Design Suite User Guide: Synthesis," UG901 [online], December 24, 2024. Available: https://docs.amd.com/r/en-US/ug901-vivado-synthesis.
[28] Namratha and Bakhar, "Power and area optimized adaptive Viterbi decoder for high-speed communication applications", International Journal of Information Technology, vol. 15, no. 1, pp. 45–52, Jan. 2023.
[29] B. N. Akash, K. M. Amogh, S. Sridhar, and P. Agarwal, "Viterbi Decoder with Configurable Constraint Length with Bit Error Correction for Satellite Communication", in Information and Communication Technology for Competitive Strategies (ICTCS 2020), 2022, pp. 697–707.
[30] M. A. Abu, H. Harun, M. Yazdi Harmin, N. I. Abdul Wahab, and M. K. Abdul Kadir, "The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model", World Journal of Engineering, vol. 13, no. 6, pp. 540–546, Jan. 2016.
[31] C. E. Stroud, L.-T. (L-T. ). Wang, and Y.-W. Chang, "Chapter 1 - Introduction," in Electronic Design Automation, L.-T. Wang, Y.-W. Chang, and K.-T. (tim) Cheng, Eds. Boston: Morgan Kaufmann, 2009, pp. 1–38. | ||||
|
Statistics Article View: 489 PDF Download: 207 |
||||
