Hardware Implementation Of Sub-Pixel Motion Estimation For HEVC Targeting FPGAs | ||
| Port-Said Engineering Research Journal | ||
| Articles in Press, Accepted Manuscript, Available Online from 21 September 2025 | ||
| Document Type: Original Article | ||
| DOI: 10.21608/pserj.2025.405566.1426 | ||
| Authors | ||
| Esraa Abdelaziz1; Emad Badry* 2; Basem El-Hady2 | ||
| 1Electrical Engineering Department, Faculty of Engineering, Suez Canal University, Ismailia, Egypt, | ||
| 2Electrical Engineering Department, Faculty of Engineering, Suez Canal University, Ismailia, Egypt | ||
| Abstract | ||
| High Efficiency Video Coding (HEVC) is the most widely used Video encoder which outperforms prior standards. In HEVC, motion estimation unit is used to exploit the temporal redundancy between successive frames. It consists of integer and sub-pixel motion estimation. This unit consumes massive hardware resources due to the intensive computations there. In this paper, we present an efficient hardware implementation of sub-pixel motion estimation unit for HEVC. It is a pipelined structure with a limited number of computations to mitigate the hardware demand for HEVC encoders. The proposed architecture was prototyped in Verilog HDL and synthesized using Altera Cyclone V FPGA. The reports show that the proposed design achieves large saving in hardware resources compared with existing approaches while preserving quality and real time consideration. It takes 1,165 LUT and 1,103 registers from Cyclone V FPGA. The proposed design can achieve a maximum frequency of 258 MHz to cope with the real-time applications. It can process 107, 60, 27 fps for 1K, 2k, and 4k resolution, respectively. It outperforms other schemes in literature with hardware reduction up to 94.15% in the number of LUTs. | ||
| Keywords | ||
| HEVC; Motion estimation; Verilog HDL; FPGA | ||
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