Coefficient Quantization and Enhanced Spectral Interpolation for Resource-Constrained Doppler Processing on FPGA | ||
| International Journal of Telecommunications | ||
| Volume 05, Issue 02, July 2025, Pages 1-17 PDF (1.27 M) | ||
| Document Type: Original Article | ||
| DOI: 10.21608/ijt.2025.433523.1139 | ||
| Authors | ||
| Abdalmaged M. Radwan* 1; Amgad A. Salama2; AbdelHamid A. Shaalan1; Nirmin M. Abdelwahab M. Abdelwahab1 | ||
| 1electronics and communication Faculty of Engineering Zagazig University | ||
| 2Department of Electrical and Computer Engineering, Concordia University, Montreal, PQ H3G 1M8, Canada; | ||
| Abstract | ||
| Accurate Doppler frequency detection is fundamental to radar systems for determining target velocity, yet a persistent trade-off exists between estimation accuracy and the computational resources required for real-time implementation, particularly on hard-ware-limited platforms like FPGAs. This study presents a novel filter bank architecture designed to resolve this conflict by employing two key methodological innovations: the strategic optimization of filter coefficient bit-width to minimize hardware resource consumption, and the development of an enhanced two-stage frequency estimation algorithm that interpolates the target Doppler shift from the outputs of adjacent filters. Simulation results and hardware implementation on a Xilinx Artix-7 FPGA demonstrate that the proposed design maintains high detection accuracy, with a stopband attenuation exceeding 50 dB and less than 0.05 dB passband deviation and reliably identifies multiple targets in low signal-to-noise ratio (SNR) environments of -20 dB, while concurrently reducing DSP block utilization by 40%. We conclude that this architecture provides a solution for high-fidelity Doppler detection in resource-constrained real-time radar applications, effectively balancing the demands of precision and efficiency. | ||
| Keywords | ||
| Doppler Radar; Filter Bank; FPGA Implementation; Resource Optimization; Signal Pro-cessing | ||
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