A HIGH-LEVEL SYNTHESIS METHODOLOGY FOR DEDICATED DSP ARCHITECTURES | ||
| The International Conference on Electrical Engineering | ||
| Article 31, Volume 2, 2nd International Conference on Electrical Engineering ICEENG 1999, November 1999, Pages 291-304 PDF (3.02 M) | ||
| Document Type: Original Article | ||
| DOI: 10.21608/iceeng.1999.62512 | ||
| Authors | ||
| E. A. TALKHAN1; ALY E. SALAMA1; F. HASHIM2 | ||
| 1Professor, Faculty of Engineering, Cairo University, Giza, Egypt. | ||
| 2Egyptian Armed Forces. | ||
| Abstract | ||
| In this work we present a proposed High-Level Synthesis (HLS) methodology for dedicated Digital Signal Processing (DSP) architectures. Starting from a purely behavior description of a DSP algorithm, the HLS subtasks namely: the Scheduling, the Allocation, and the Binding are performed to generate an optimized Register Transfer Level (RTL) data path structure which implements the intended behavior while satisfying the .timing constraints. The Scheduling and the Allocation subtasks are solved simultaneously in terms of an Integer Linear Programming (ILP) feasibility model. The Binding subtask is solved using a Weighted Bipartite Matching (WBM) algorithm. A 4-point FIR filter is used to demonstrate our methodology in a step wise fashion, from the initially specified behavior to the finally synthesized structure. Simulation results have proved that the finally synthesized data path is truly implementing the initially specified behavior and satisfying the timing constraints. | ||
| Keywords | ||
| high-level synthesis; Digital Signal Processing; register transfer level; time-constrained optimization; weighted assignment; hardware description language | ||
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