Speeding-up MOS Circuits Containing Stacks | ||||
| Port-Said Engineering Research Journal | ||||
| Article 14, Volume 16, Issue 1, March 2012, Page 165-175 PDF (1023.33 K) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/pserj.2012.106080 | ||||
 View on SCiNiTO | ||||
| Abstract | ||||
| MOS circuits such as NAND and NOR gates may contain stacks of NMOS and PMOS transistors especially with wide fan-in. The main problem associated with these stacks is the relatively slow response due to the relatively large RC time constant associated with charging or discharging the parasitic capacitances at the output node as well as the internal nodes of the circuit. In this paper, a proposed technique will be presented in order to reduce the time delay of these circuits. The proposed technique is analyzed quantitatively and a compact form for the percentage reduction in the discharging time delay is derived and the optimum configuration for the proposed circuit is decided on. Simulation results adopting the 0.13 µm CMOS technology reveals that about 40% of the time delay can be saved | ||||
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