EFFICIENT HARDWARE IMPLEMENATATIONS OF FEEDFORWARD NEURAL NETWORKS USING FIELD PROGRAMMABLE GATE ARRAY
Essai, M., Magdy, M. (2018). EFFICIENT HARDWARE IMPLEMENATATIONS OF FEEDFORWARD NEURAL NETWORKS USING FIELD PROGRAMMABLE GATE ARRAY. EKB Journal Management System, 46(No 5), 539-555. doi: 10.21608/jesaun.2018.110510
Mohamed H. Essai; Marina Magdy. "EFFICIENT HARDWARE IMPLEMENATATIONS OF FEEDFORWARD NEURAL NETWORKS USING FIELD PROGRAMMABLE GATE ARRAY". EKB Journal Management System, 46, No 5, 2018, 539-555. doi: 10.21608/jesaun.2018.110510
Essai, M., Magdy, M. (2018). 'EFFICIENT HARDWARE IMPLEMENATATIONS OF FEEDFORWARD NEURAL NETWORKS USING FIELD PROGRAMMABLE GATE ARRAY', EKB Journal Management System, 46(No 5), pp. 539-555. doi: 10.21608/jesaun.2018.110510
Essai, M., Magdy, M. EFFICIENT HARDWARE IMPLEMENATATIONS OF FEEDFORWARD NEURAL NETWORKS USING FIELD PROGRAMMABLE GATE ARRAY. EKB Journal Management System, 2018; 46(No 5): 539-555. doi: 10.21608/jesaun.2018.110510

EFFICIENT HARDWARE IMPLEMENATATIONS OF FEEDFORWARD NEURAL NETWORKS USING FIELD PROGRAMMABLE GATE ARRAY

JES. Journal of Engineering Sciences
Article 1, Volume 46, No 5, September and October 2018, Page 539-555  XML PDF (823.92 K)
Document Type: Research Paper
DOI: 10.21608/jesaun.2018.110510
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Authors
Mohamed H. Essai email orcid 1; Marina Magdy2
1Electrical Eng. Depart, Faculty of Engineering-Qena, Al-Azhar University, Egypt
2Electronics & Communications Engineering Department, Higher Institute of Engineering and Technology, Luxor – El Tod, Egypt
Abstract
Hardware implementation of Artificial Neural Network (ANNs) depends mainly on the efficient implementation of the activation functions. Field Programmable Gate Array is the most appropriate tool for hardware implementation of ANNs. In this paper we introduce FPGA-based hardware implementation of ANNs using five different activation functions. These implemented NNs are described using Very High Speed Integrated Circuits Hardware Description Language (VHDL) and carried out by Digilent Basys 2 Spartan-3E FPGA platform from Xilinx. The performances of the implemented NNs were investigated in terms of area efficient implementation, and correct prediction percentages for solving XOR, and Full-Adder problems.
Keywords
Artificial system; VHDL; FFNN; FPGA; Back-propagation; Activation function
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