HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES
Taher, M., Aboulwafa, M., Abdelwahab, A., Saad, E. (2006). HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES. EKB Journal Management System, 34(No 4), 1283-1292. doi: 10.21608/jesaun.2006.110784
M. Taher; M. Aboulwafa; A. Abdelwahab; E. M. Saad. "HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES". EKB Journal Management System, 34, No 4, 2006, 1283-1292. doi: 10.21608/jesaun.2006.110784
Taher, M., Aboulwafa, M., Abdelwahab, A., Saad, E. (2006). 'HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES', EKB Journal Management System, 34(No 4), pp. 1283-1292. doi: 10.21608/jesaun.2006.110784
Taher, M., Aboulwafa, M., Abdelwahab, A., Saad, E. HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES. EKB Journal Management System, 2006; 34(No 4): 1283-1292. doi: 10.21608/jesaun.2006.110784

HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES

JES. Journal of Engineering Sciences
Article 13, Volume 34, No 4, July and August 2006, Page 1283-1292  XML PDF (87.7 K)
Document Type: Research Paper
DOI: 10.21608/jesaun.2006.110784
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Authors
M. Taher email 1; M. Aboulwafa* 2; A. Abdelwahab* 2; E. M. Saad* 2
1Electronic Engineer in Tibben Institute for Metallurgical Studies
2Faculty of Engineering, Helwan University, Cairo, Egypt
Abstract
In this paper, single-precision floating-point IEEE-754 standard Adder/Subtractor and Multiplier modules with high speed and area efficient are presented. These modules are designed, simulated, synthesized, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of normalization unit at the singleprecision floating-point multiplier and adder/Subtractor modules on the area, and speed is explained.
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