An 8-Bit Full-Adder Implementation Using Single Electron Tunneling (SET) Technology. | ||||
| MEJ- Mansoura Engineering Journal | ||||
| Article 13, Volume 32, Issue 2, June 2007, Page 79-85 PDF (284.26 K) | ||||
| Document Type: Research Studies | ||||
| DOI: 10.21608/bfemu.2020.128510 | ||||
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| Authors | ||||
| Sameh Rehan* 1; Eman Almetwaly2 | ||||
| 1(Senior Member IEEE) Communications and Electronics Engineering Department Faculty of Engineering, Mansoura University Mansoura, EGYPT 35516 | ||||
| 2Communications and Electronics Engineering Department Faculty of Engineering, Mansoura University Mansoura, EGYPT 35516 | ||||
| Abstract | ||||
| Single Electron Tunneling (SET) devices have come to be considered as promising candidates for future ultra-low power and high-density integrated circuits. Their potential for ultra-low power is related to that the operation is based on only a few electrons. The term Single Electron Tunneling (SET) technology has been selected for devices sensitive to the manipulation of a single electron even if the device itself requires in fact few electrons. Besides, SET provides a simple and elegant solution for implementing threshold Logic Gates (TLGs). This paper presents a SET TLG one-bit full-adder implemented in SET technology. The paper then introduces the design and implementation of an 8-bit SET TLG full-adder and presents its SIMON 2 simulation results. | ||||
| Keywords | ||||
| Single Electron Tunneling (SET); Threshold Logic Gate (TLG); Full Adder (FA) | ||||
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