FPGA versus ASIC Implementation of Radix-4 Scalable Montgomery Modular Multiplier.
Ibrahim, A., El-Simary, H., Nassar, A. (2020). FPGA versus ASIC Implementation of Radix-4 Scalable Montgomery Modular Multiplier.. EKB Journal Management System, 31(3), 27-33. doi: 10.21608/bfemu.2020.129985
Atef A. Ibrahim; Hamed A. El-Simary; Amen M. Nassar. "FPGA versus ASIC Implementation of Radix-4 Scalable Montgomery Modular Multiplier.". EKB Journal Management System, 31, 3, 2020, 27-33. doi: 10.21608/bfemu.2020.129985
Ibrahim, A., El-Simary, H., Nassar, A. (2020). 'FPGA versus ASIC Implementation of Radix-4 Scalable Montgomery Modular Multiplier.', EKB Journal Management System, 31(3), pp. 27-33. doi: 10.21608/bfemu.2020.129985
Ibrahim, A., El-Simary, H., Nassar, A. FPGA versus ASIC Implementation of Radix-4 Scalable Montgomery Modular Multiplier.. EKB Journal Management System, 2020; 31(3): 27-33. doi: 10.21608/bfemu.2020.129985

FPGA versus ASIC Implementation of Radix-4 Scalable Montgomery Modular Multiplier.

MEJ- Mansoura Engineering Journal
Article 5, Volume 31, Issue 3, September 2006, Page 27-33  XML PDF (217.68 K)
Document Type: Research Studies
DOI: 10.21608/bfemu.2020.129985
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Authors
Atef A. Ibrahim* 1; Hamed A. El-Simary2; Amen M. Nassar3
1Electronics Research Institute, Cairo, Egypt,
2Electronics Research Institute, Cairo, Egypt.
3Cairo University, Cairo, Egypt
Abstract
Traditional ASIC implementations have the well known draw-back of reduced flexibility compared to software implementations. Since modem security protocols are increasingly defined to be algorithm independent, a high degree of flexibility with respect to the cryptographic algorithms is desirable. A promising solution which combines high flexibility with the speed and physical security of traditional hardware is the implementation of cryptographic algorithms on reconfigurable devices such as FPGA. In this paper we compare - in terms of area and speed-FPGA Implementation of radix-4 scalable Montgomery modular multiplier using encoding technique (15] with ASIC implementation for different word sizes of operands. The experimental data were generated using Mentor Graphics CAD tools. 
 
Keywords
Montgomery Multiplication; Scalability; FPGA Implementation; ASIC Implementation; Cryptography
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