FPGA Implementation of a PCM Decoder for Range Telemetry System with Block Code | ||||
| Journal of the ACS Advances in Computer Science | ||||
| Article 5, Volume 2, Issue 1, 2008, Page 73-84 PDF (1.24 MB) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/asc.2008.148471 | ||||
 View on SCiNiTO | ||||
| Abstract | ||||
| Pulse Code Modulation (PCM) Telemetry is a way of acquiring data in one location, converting the data samples to digital words, encoding the data in a serial format, and transmitting it to another location for decoding and analysis. Field programmable circuits now have capacities that enhance the telemetry systems capabilities. This paper demonstrates the simulation and implementation of a dual coding algorithm for PCM decoder. The hardware implementation is based on Industry Standard Architecture (ISA) interface. Dual coding capability that switches between NRZ and Manchester coding algorithm is adopted to enhance security performance. Small size and high performance are obtained using ACTEL FPGA. Simulation results are compared with practical measurements of the designed decoder. | ||||
| Keywords | ||||
| Decoder; PCM; FPGA; ACTEL and IS | ||||
|
Statistics Article View: 79 PDF Download: 282 |
||||
