Design and Implementation of Time Variable Gain Amplifier (TVG) using FPGA | ||||
| The International Undergraduate Research Conference | ||||
| Volume 5, Issue 5, 2021, Page 329-332 PDF (1.23 MB) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/iugrc.2021.246366 | ||||
 View on SCiNiTO | ||||
| Authors | ||||
| Ayman El-Gebally; Ahmed Mohey Dwedar; Asem Wageh; Hossam Sabry Tork; Adel Abdallah; Ahmed Yasser | ||||
| MTC, Egypt. | ||||
| Abstract | ||||
| In this paper, design a time variable gain control is proposed using FPGA VHDL codes. For echo sounder and sonar systems, it is necessary to amplify the returned echo from the targets. Using the Altera DE1-SoC development kit for controlling the gain control pin of the amplifier make it flexible to do more than one process on same board. The algorithm used in this paper make it easy for changing the value of each step of TVG. TVG VHDL code is designed for 0.1 mS period pulse with 10 Hz. Also, considering the effect of high amplitude echo with high delay time on receiver saturation, the algorithm is designed with hold state for avoiding this effect. The TVG code timing is synchronous with the transmitted signals. The VHDL code is designed using Quartus software and being simulated using Modelsim software. Their combination results are efficient to be used for controlling Digital to Analog Converter (DAC) amplifier which used to generate amplified signal. | ||||
| Keywords | ||||
| Time variable gain; TVG amplifier; TVG VHDL code; FPGA; Receiver saturation; DAC | ||||
|
Statistics Article View: 119 PDF Download: 96 |
||||
