DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA
Shehata, K., Hamdy, N., Elagooz, S., Helmy, M. (2003). DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA. EKB Journal Management System, 10(10th International Conference On Aerospace Sciences & Aviation Technology), 717-727. doi: 10.21608/asat.2013.24692
Khaled Shehata; Nabil Hamdy; Salah Elagooz; M. Helmy. "DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA". EKB Journal Management System, 10, 10th International Conference On Aerospace Sciences & Aviation Technology, 2003, 717-727. doi: 10.21608/asat.2013.24692
Shehata, K., Hamdy, N., Elagooz, S., Helmy, M. (2003). 'DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA', EKB Journal Management System, 10(10th International Conference On Aerospace Sciences & Aviation Technology), pp. 717-727. doi: 10.21608/asat.2013.24692
Shehata, K., Hamdy, N., Elagooz, S., Helmy, M. DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA. EKB Journal Management System, 2003; 10(10th International Conference On Aerospace Sciences & Aviation Technology): 717-727. doi: 10.21608/asat.2013.24692

DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA

International Conference on Aerospace Sciences and Aviation Technology
Article 47, Volume 10, 10th International Conference On Aerospace Sciences & Aviation Technology, May 2003, Page 717-727  XML PDF (2.27 MB)
Document Type: Original Article
DOI: 10.21608/asat.2013.24692
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Authors
Khaled Shehata1; Nabil Hamdy2; Salah Elagooz3; M. Helmy4
1Assoc. Prof., AAST Communication Dept.
2MOD Signal Dept.
3Assoc. Prof., MTC Communication Dept.
4MTC Communication Dept.
Abstract
In this paper the design and implementation of the International Data Encryption Algorithm (IDEA) key schedule is presented. The IDEA key schedule takes 128-bit input key and returns 52 subkeys each of 16 bits during the encryption or the decryption operation. The key schedule includes the design of the inverse modulo (216+ 1) multiplier and the
inverse modulo 216 adder. The inverse modulo multiplier circuit is used to generate 18 inverse multiplicative keys and the inverse modulo adder circuit is used to generate 18 inverse additive keys. The inverse multiplicative key is calculated through multiplying the key to the power (216- 1) modulo (216+ 1). A 16 bit counter controls the inverse modulo multiplier circuit during the modulo multiplication process. A zero state problem is denoted during the generation of the inverse multiplicative keys because 216 is treated as zero during the modulo (216+ 1) multiplication in the encryption process. The IDEA key schdule is implemented on Xilinx FPGA Spartan II family and the target chip is XC2S100-5PQ208C.
Keywords
FPGA; Modulo (216 + 1) multiplier; IDEA; Inverse Modulo (216 + 1)multiplication; Key Schedule; Implementation
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