Architecture for the BIST Boundary Scan | ||||
| International Conference on Aerospace Sciences and Aviation Technology | ||||
| Article 73, Volume 10, 10th International Conference On Aerospace Sciences & Aviation Technology, May 2003, Page 1057-1067 PDF (2.08 MB) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/asat.2019.24728 | ||||
 View on SCiNiTO | ||||
| Author | ||||
| Mohamed H. El-Mahlawy | ||||
| Egyptain Armed Forced. | ||||
| Abstract | ||||
| The boundary scan (BS) technique, formally known as IEEE-1149.1 Standard, offers a convenient alternative to physical probing by effectively migrating the test probe circuitry into the chip which enables a non-contact method of accessing chip pins for testing. In this paper, the incorporation of Built-In Self-Test (BIST) capabilities into the boundary scan architecture is presented. The Boundary Scan Register (BSR) input cells have been con-figured to operate as a Test Pattern Generator (TPG) in the BIST mode. The BSR input and output cells have been configured to operate as an Muti-Input Shift Register (MISR) in the BIST mode. The Tape Controller (TAPC) controls the BIST process. Instructions for BIST process are proposed. This configuration supports BIST for both the cascaded and non-cascaded input and output cells of the BSR. | ||||
|
Statistics Article View: 110 PDF Download: 262 |
||||
