AN IMPLEMENTATION OF THE RUN-LENGTH ENCODE ALGORITHM USING FPGA | ||||
International Conference on Aerospace Sciences and Aviation Technology | ||||
Article 59, Volume 11, ASAT Conference, 17-19 May 2005, May 2011, Page 947-954 PDF (1.3 MB) | ||||
Document Type: Original Article | ||||
DOI: 10.21608/asat.2011.27208 | ||||
View on SCiNiTO | ||||
Authors | ||||
Gouda I. Salama1; Fawzy ELtohamy Hassan1; M. Sharrawy2; Ramy M. Bahy1 | ||||
1Egyptian Armed Forces. | ||||
2Faculty of Computers and Information, Helwan University, Egypt. | ||||
Abstract | ||||
This paper presents a real time implementation of Run-Length Encode (RLE) using FPGA as one of image compression algorithms. The RLE algorithm can be implemented either on commercial DSP or as an ASIC but due to the huge development in the FPGA field, it is recommended to use the FPGA technology. The design steps from design entry to files which are needed for the download process are developed. | ||||
Keywords | ||||
Run-Length Encode; FPGA; Image compression | ||||
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