Design for Testability Technique for Microcontroller | ||||
| The International Conference on Electrical Engineering | ||||
| Article 63, Volume 8, 8th International Conference on Electrical Engineering ICEENG 2012, May 2012, Page 1-18 PDF (762.6 K) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/iceeng.2012.30809 | ||||
 View on SCiNiTO | ||||
| Authors | ||||
| Sherif I. Morsy; Mohamed H. El-Mahlawy; Gouda I. Mohamed | ||||
| Egyptian Armed Forces. | ||||
| Abstract | ||||
| Testing of embedded system including microcontroller is difficult task with external Automatic Test Equipment (ATE). Therefore, empowering the microcontroller to test itself as software-based self-testing (SBST) looks the suitable solution like the microprocessor testing. Practically, the SBST is not suitable for microcontroller testing. It utilizes large space area in the program memory inside the microcontroller that has limited space area in the available memory. Also, it cannot test all microcontroller internal modules and when it test internal modules it cannot make sure that the General Purpose Input Output (GPIO) of the microcontroller work probably without using external ATE. So the Design for Testability (DFT) methodology that uses Instruction Set Architecture (ISA) of the microcontroller family to generate test subroutines and for the Test Pattern Generator (TPG) and part of the Built-In Self-Test (BIST) control unit and uses the external ATE for the other part of the BIST control unit and for the test response compaction (TRC) and evaluation. This paper introduces a hybrid testing methodology that combines both SBST and hardware-based self-test (HBST) for microcontroller testing as an efficient DFT methodology. It introduces for either in the field or as part of a production test of a microcontroller as an example of the system of chip (SoC). This DFT methodology is based on divide and conquer algorithm and requires knowledge of the ISA of the microcontroller to test not only the embedded processor found in microcontroller but also test other peripherals found in it using brute force technique. The comparison between the SBST and the presented hybrid methodology is based on memory utilization, number of clock cycles that was taken to complete each test and the number of modules that can be tested using each of them. Experimental results indicate that the presented methodology is superior in memory utilization, test time and can test all microcontroller modules for both 18F4X2 and 16F87X families. | ||||
| Keywords | ||||
| Design-for-Tetability (DFT); Built-In Self-Test (BIST) | ||||
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