Assertion based HDL-models testing for SoC components
Hahanov, V., Litvinova, E., Gharibi, W., Guz, O., Umerah, N., Yves, T. (2010). Assertion based HDL-models testing for SoC components. EKB Journal Management System, 7(7th International Conference on Electrical Engineering ICEENG 2010), 1-14. doi: 10.21608/iceeng.2010.33006
Vladimir Hahanov; Eugenia Litvinova; Wajeb Gharibi; Olesya Guz; Ngene Christopher Umerah; Tiecoura Yves. "Assertion based HDL-models testing for SoC components". EKB Journal Management System, 7, 7th International Conference on Electrical Engineering ICEENG 2010, 2010, 1-14. doi: 10.21608/iceeng.2010.33006
Hahanov, V., Litvinova, E., Gharibi, W., Guz, O., Umerah, N., Yves, T. (2010). 'Assertion based HDL-models testing for SoC components', EKB Journal Management System, 7(7th International Conference on Electrical Engineering ICEENG 2010), pp. 1-14. doi: 10.21608/iceeng.2010.33006
Hahanov, V., Litvinova, E., Gharibi, W., Guz, O., Umerah, N., Yves, T. Assertion based HDL-models testing for SoC components. EKB Journal Management System, 2010; 7(7th International Conference on Electrical Engineering ICEENG 2010): 1-14. doi: 10.21608/iceeng.2010.33006

Assertion based HDL-models testing for SoC components

The International Conference on Electrical Engineering
Article 47, Volume 7, 7th International Conference on Electrical Engineering ICEENG 2010, May 2010, Page 1-14  XML PDF (437.82 K)
Document Type: Original Article
DOI: 10.21608/iceeng.2010.33006
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Authors
Vladimir Hahanov1; Eugenia Litvinova1; Wajeb Gharibi2; Olesya Guz3; Ngene Christopher Umerah1; Tiecoura Yves1
1Kharkov National University of Radioelectronics, Kharkov, Ukraine.
2Jazan University, Kingdom of Saudi Arabia.
3Donetsk Academy of Road Transport, Donetsk, Ukraine.
Abstract
Abstract:
The testing and verification technology for system HDL models, focused to the
significant improvement of the quality of design components for digital systems on
chips and reduction the development time (time-to-market) by using the simulation
environment, testable analysis of the logical structure HDL-program and the optimal
placement of assertion engine is proposed.
Keywords
Testing; verification; HDL-model; assertion engine
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