General Structure Design and simulation for Image Processing | ||||
| The International Conference on Electrical Engineering | ||||
| Article 62, Volume 7, 7th International Conference on Electrical Engineering ICEENG 2010, May 2010, Page 1-16 PDF (550.93 K) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/iceeng.2010.33034 | ||||
 View on SCiNiTO | ||||
| Authors | ||||
| Wael Wasfy; Hong Zheng; Wu Xinghua; Li Jun | ||||
| School of Automation Science and Electrical Engineering, Beijing University of Aeronautics and Astronautics, Beijing, 100191, P. R. China. | ||||
| Abstract | ||||
| Abstract: Designing a general structure for fast image processing algorithms to compute the image intensity for low level 3x3 algorithms having the same parallel calculation method but with different kernel is our goal in this paper. Using DSP slice module inside the FPGA was an objective task to get the advantage of it as a faster, accurate, higher number of bits in calculations and different calculated equation maneuver capabilities. Using the remade design scheme can solve many problems such as redesign time consumption, increasing the calculation accuracy by using high number of bits in calculations more than the regular logic gates, saving FPGA resources is one of the advantages we got by using the general structure design especially if we need to make more than 3x3 low level algorithm for the same project we can select which algorithm to be calculated at certain time for the same structure as we take an example in this paper by selecting between Gaussian filter and Sobelx edge detector as an example. The General structure is capable to be modified to add other algorithms which have the same calculation methods. Other designers as mentioned later an example on this paper uses separate fixed design for each algorithm with maximum 12bit calculation accuracy. | ||||
| Keywords | ||||
| Image processing; FPGA; Embedded processor | ||||
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