An Implementation of the Run-Length Decode Algorithm using FPGA
Salama, G., Hassan, F., Bahy, R., Ibrahim, S. (2006). An Implementation of the Run-Length Decode Algorithm using FPGA. EKB Journal Management System, 5(5th International Conference on Electrical Engineering ICEENG 2006), 1-8. doi: 10.21608/iceeng.2006.33505
Gouda Ismail Salama; Fawzy ELtothamy Hassan; Ramy Mohammed Bahy; Sameh shawky Ibrahim. "An Implementation of the Run-Length Decode Algorithm using FPGA". EKB Journal Management System, 5, 5th International Conference on Electrical Engineering ICEENG 2006, 2006, 1-8. doi: 10.21608/iceeng.2006.33505
Salama, G., Hassan, F., Bahy, R., Ibrahim, S. (2006). 'An Implementation of the Run-Length Decode Algorithm using FPGA', EKB Journal Management System, 5(5th International Conference on Electrical Engineering ICEENG 2006), pp. 1-8. doi: 10.21608/iceeng.2006.33505
Salama, G., Hassan, F., Bahy, R., Ibrahim, S. An Implementation of the Run-Length Decode Algorithm using FPGA. EKB Journal Management System, 2006; 5(5th International Conference on Electrical Engineering ICEENG 2006): 1-8. doi: 10.21608/iceeng.2006.33505

An Implementation of the Run-Length Decode Algorithm using FPGA

The International Conference on Electrical Engineering
Article 8, Volume 5, 5th International Conference on Electrical Engineering ICEENG 2006, May 2006, Page 1-8  XML PDF (289.43 K)
Document Type: Original Article
DOI: 10.21608/iceeng.2006.33505
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Authors
Gouda Ismail Salama1; Fawzy ELtothamy Hassan1; Ramy Mohammed Bahy2; Sameh shawky Ibrahim3
1Ph.D., Egyptian Armed Forces.
2M.Sc., Egyptian Armed Forces.
3B.Sc., Egyptian Armed Forces.
Abstract
Abstract:
This paper presents a real time implementation of Run-Length Decode (RLD) using FPGA as
one of image decompression algorithms. The RLD algorithm is the decoder of the Run-
Length Encode. RLD can be implemented either on commercial DSP or as an ASIC but due
to the huge development in the FPGA field, it is recommended to use the FPGA technology.
The design steps from design entry to files which are needed for the download process are
developed. Also, the method of testing the downloaded design is explained.
Keywords
Run-Length Decode; FPGA; Image compression
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