DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA
Rohiem, A., Hassan, K., El-Amin, A. (2006). DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA. EKB Journal Management System, 5(5th International Conference on Electrical Engineering ICEENG 2006), 1-24. doi: 10.21608/iceeng.2006.33547
Alaa El Din Rohiem; Kamel Mohamed Hassan; Ahmed M. El-Amin. "DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA". EKB Journal Management System, 5, 5th International Conference on Electrical Engineering ICEENG 2006, 2006, 1-24. doi: 10.21608/iceeng.2006.33547
Rohiem, A., Hassan, K., El-Amin, A. (2006). 'DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA', EKB Journal Management System, 5(5th International Conference on Electrical Engineering ICEENG 2006), pp. 1-24. doi: 10.21608/iceeng.2006.33547
Rohiem, A., Hassan, K., El-Amin, A. DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA. EKB Journal Management System, 2006; 5(5th International Conference on Electrical Engineering ICEENG 2006): 1-24. doi: 10.21608/iceeng.2006.33547

DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA

The International Conference on Electrical Engineering
Article 25, Volume 5, 5th International Conference on Electrical Engineering ICEENG 2006, May 2006, Page 1-24  XML PDF (351.16 K)
Document Type: Original Article
DOI: 10.21608/iceeng.2006.33547
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Authors
Alaa El Din Rohiem; Kamel Mohamed Hassan; Ahmed M. El-Amin
Abstract
ABSTRACT:
In this paper, we present developed design procedures for a pipelined Advanced
Encryption Standard [AES] encryption algorithm using Field Programmable Gate Array
[FPGA].The design procedures starting from entering the design parameters until
functional simulation and testing have been introduced in this paper. System throughput
of 1.408Gbps has been achieved, whereas the published results for similar systems are
much less than this rate [4-7].
Keywords
FPGA; AES; VHDL; Encryption; decryption
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