NEW AUTOMATIC TESTING ARCHITECTURE FOR INTEGRATED CIRCUITS | ||||
| The International Conference on Electrical Engineering | ||||
| Article 31, Volume 5, 5th International Conference on Electrical Engineering ICEENG 2006, May 2006, Page 1-14 PDF (518.05 K) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/iceeng.2006.33556 | ||||
 View on SCiNiTO | ||||
| Authors | ||||
| Sherif Anas; Mohamed H. El-Mahlawy; Ehab A. El-Sehely; Al-Emam S. Ragab | ||||
| Egyptian Armed Forces. | ||||
| Abstract | ||||
| ABSTRACT In this paper, a complete example for BIST (Built-In Self-Test) boundary scan architecture and 16-bit multiplier as the CUT is presented. Adding BIST boundary scan capabilities to the digital VLSI integrated circuit design makes the electronic card testable from five pins TMS, TCK, TDI, TDO and TRST* that is optional. The simulation and then design download are presented on the Spartan Xilinx X2C100 chip. The hardware implementation is tested using the interfacing through the parallel port of the personal computer that supplies required five control pins. This approach will lead to the concept of the portable ATE (Automatic Test Equipment). All required test circuitry is embedded in the integrated circuits and the control of the test circuitry is supplied from the TAP (Test Access Port) controller. Finally, the TAP controller is controlled from the parallel port of the personal computer. So, the personal computer is used as a master controller and the TAP controller is used as a slave controller. The presented idea of the new BIST testing architecture solves the testing problem of the digital VLSI circuits using the traditional ATE. | ||||
| Keywords | ||||
| Design-for-test (DFT); Automatic Test Equipment; Testing of electronic circuits | ||||
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