A novel design and implementation of FPGA based 3D-CORDIC processor
M., A., M., A., A., A., Rashed, A. (2008). A novel design and implementation of FPGA based 3D-CORDIC processor. EKB Journal Management System, 6(6th International Conference on Electrical Engineering ICEENG 2008), 1-18. doi: 10.21608/iceeng.2008.34337
Al-Homosy , G. M.; Abass, Y. M.; Al-Kholy, S. A.; A . M . Rashed. "A novel design and implementation of FPGA based 3D-CORDIC processor". EKB Journal Management System, 6, 6th International Conference on Electrical Engineering ICEENG 2008, 2008, 1-18. doi: 10.21608/iceeng.2008.34337
M., A., M., A., A., A., Rashed, A. (2008). 'A novel design and implementation of FPGA based 3D-CORDIC processor', EKB Journal Management System, 6(6th International Conference on Electrical Engineering ICEENG 2008), pp. 1-18. doi: 10.21608/iceeng.2008.34337
M., A., M., A., A., A., Rashed, A. A novel design and implementation of FPGA based 3D-CORDIC processor. EKB Journal Management System, 2008; 6(6th International Conference on Electrical Engineering ICEENG 2008): 1-18. doi: 10.21608/iceeng.2008.34337

A novel design and implementation of FPGA based 3D-CORDIC processor

The International Conference on Electrical Engineering
Article 90, Volume 6, 6th International Conference on Electrical Engineering ICEENG 2008, May 2008, Page 1-18  XML PDF (695.06 K)
Document Type: Original Article
DOI: 10.21608/iceeng.2008.34337
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Authors
Al-Homosy , G. M.1; Abass, Y. M.2; Al-Kholy, S. A.1; A . M . Rashed3
1Physics & Mathematics Dept, Suez Canal University.
2Physics Dept, Suez Canal University.
3Systems & Computers Dept, Al-Azhar University.
Abstract
Abstract:
A new complete design and implementation of FPGA-based Three Dimensions
CORDIC processor (3D-CORDIC)is introduced. Efficient mappings on FPGA have
been performed leading to the fastest implementations. Simulation process have been
performed for the proposed 3D-CORDIC processor using ModelSim SE tools of Mentor
Graphics simulations and the MATLAB Software simulations, a good agreement of the
proposed processor performance has been achieved. The 3D-CORDIC processor
architecture has been implemented with 12 bit word-length in Xilinx Spartan-II series
field programmable gates arrays (FPGA). The 3D-CORDIC processor use only 37 % of
SLICEs and 52 % of IOBs with maximum clock frequency 116 MHz, which is suitable
for many CORDIC processor applications.
Keywords
FPGA; CORDIC; VHDL; 3D-CORDIC PROCESSOR
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