ENHANCED PERFORMANCE OF COMPLEMENTARY GALLIUM ARSENIDE (CGAAS) CIRCUITS | ||||
| The International Conference on Electrical Engineering | ||||
| Article 37, Volume 2, 2nd International Conference on Electrical Engineering ICEENG 1999, November 1999, Page 357-367 PDF (1.64 MB) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/iceeng.1999.62521 | ||||
 View on SCiNiTO | ||||
| Authors | ||||
| Khaled Ali Shehata1; Douglas J. Fouts2 | ||||
| 1Manager of AOI VLSI Design Center, Cairo, Egypt | ||||
| 2ECE Department, NPS, Monterey, CA93943 | ||||
| Abstract | ||||
| The theory, design, imple -nentation and evaluation of Two-Phase Dynamic FET Logic (TPDL), a logic fami y that is compatible with the existing Complementary Gallium Arsenide (CGaAs) fabrication process and design tools, is documented. Several different logic functions have been implemented in both TPDL and static logic. A performance comparison between the TPDL and static logic circuits is also performed. TPDL circ Jits are much faster than the static circuits performing the same function becaus a the former do not use PFETs for logic expression evaluation, only for precharging. Also, TPDL circuits co: •sumes less power than static circuits because they have no short-circuit current and a reduced leakage current. The maximum operating frequency of the TPDL circuits is 2.38 GHz and they have the lowest poorer-delay product ever reported in this technology (0.01mW/gate/MHz). | ||||
| Keywords | ||||
| TPDL; CgaAs; Dynamic Logic; VLSI and Domino Logic | ||||
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