A Run-Time Program Phase Detection Technique for Optimizing Per-Phase L2 Cache Demand | ||||
The Egyptian International Journal of Engineering Sciences and Technology | ||||
Article 1, Volume 20, EIJEST, Vol. 20, 2016, September 2016, Page 1-9 PDF (415.59 K) | ||||
Document Type: Original Article | ||||
DOI: 10.21608/eijest.2016.97168 | ||||
View on SCiNiTO | ||||
Authors | ||||
I Ziedan* 1; H Shehata2; S Seraga2 | ||||
1Computers and Systems Department, Zagazig University, Zagazig 44519, Egypt. | ||||
2Computers and Systems Department, Zagazig University, Zagazig 44519, Egypt | ||||
Abstract | ||||
Understanding program behavior is at the foundation of computer architecture and program optimization. Programs pass through different behaviors where their performance characteristics and hardware resource requirements vary. Program phase detection and classification research aiming to understand the program timevarying behavior, can unlock a lot of phase-based optimizations which are specially tailored to improve the performance of each individual program phase. In this paper, we introduce an efficient run-time phase detection and classification technique, based on tracking changes in the L2 cache access pattern of different portions in the program execution. The proposed technique monitors a running program and keeps track what phase the running program is currently executing, with no need to recompile the tracked program, and with execution time overhead of 4%, on average. Performance Monitoring Unit (PMU) is exploited to sample the memory addresses causing L1 data cache misses. This profiling data is used to construct the Cache Access Signature Vectors (CASVs) that accurately reflect the L2 cache access patterns for each interval of execution. By comparing CASVs, the proposed technique classifies the program into a set of stable phases with high degree of intraphase homogeneity. Our evaluation shows that phase changes detected by our technique have strong correlation with the variation in Instruction Per Cycle (IPC). Furthermore, our technique can contribute in reducing L2 cache miss rates, and optimizing L2 cache utilization, through its direct capability of estimating per-phase L2 cache demand | ||||
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