A Low Power and Flat Gain CMOS RFPA For UWB Applications Using Complementary Current Reuse Stage | ||||
SVU-International Journal of Engineering Sciences and Applications | ||||
Volume 6, Issue 1, June 2025, Page 61-68 PDF (551.04 K) | ||||
Document Type: Original research articles | ||||
DOI: 10.21608/svusrc.2024.337701.1249 | ||||
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Authors | ||||
Ayman Mahmoud Ismaiel ![]() ![]() ![]() ![]() | ||||
1Electrical Engineering Department, Faculty of Engineering, South Valley University, Qena 83523, Egypt | ||||
2Egypt-Japan University of Science and Technology, Alexandria 21934, Egypt | ||||
Abstract | ||||
A low power, high linearity, and flat gain ultra-wideband radio frequency power amplifier (UWB RFPA) circuit design for 3.1-10.6 GHz is proposed in 0.18 um CMOS process. To achieve linear and flat gain over the whole frequency band, the UWB RFPA is built using two stage circuits. A complementary Current-reused topology is applied to minimize the number of coils and present self-bias with improved power gain for the driver stage in the whole frequency band. In the meantime, each RF transistor's input and output terminals have a feedback network coupled by a resistor and a capacitor in series to enhance the gain flatness throughout the entire frequency range. The simulation results demonstrate that the UWB RFPA achieves the saturation output power of 15 dBm at 7.5 GHz. The UWB RFPA has a flat power gain (||S21||) of 21±0.5dB, output 1-dB compression point of 11±0.5dBm, maximum power-added efficiency (PAE) of 22±2%. The amplifier exhibits input and output reflection coefficients of less than -10dB and -10±3dB, respectively. Additionally, the reverse isolation is approximately -40dB, with a power consumption of 23.4 mW and 47 mW from a 1.8 V supply for driver stage and power stage respectively. | ||||
Keywords | ||||
CMOS Amplifier; Feedback Network; Power Added Efficiency (PAE); linearity; Self-Bias | ||||
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