The Single Bit Request Grant (SBRG) Scheduling Algorithm for Input-Queued ATM Switches | ||||
| Menoufia Journal of Electronic Engineering Research | ||||
| Article 6, Volume 29, Issue 2, July 2020, Page 41-48 PDF (880.82 K) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/mjeer.2020.103271 | ||||
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| Authors | ||||
| Mervat Said; Zeiad El-Saghir; Nawal EL-Fishawy | ||||
| Computer Science and Engineering Dept., Faculty of Electronic Engineering, Menoufia University, Egypt. | ||||
| Abstract | ||||
| In this paper, we propose an efficient single-iteration single-bit request scheduling algorithm for input-queued ATM switches that based on a new arbitration technique called the Single Bit Request Grant (SBRG) algorithm. The operation of the SBRG depends on the concept known as “the preferred input-output pairs first”, and the arbitration requests starts from switch output ports to reduce the number of issued request signals. Compared to other single-iteration algorithms, simulation results show that the SBRG maximizes the match size and improves the switch delay/throughput performance, especially when the load increases. Also, the proposed algorithm reduces the complexity of some of the existing algorithms by decreasing the number of input-output transferred messages, and by the absence of any encoding/decoding mechanism that can be used in some existing algorithms to reduce the size of request signals to one bit. | ||||
| Keywords | ||||
| Input-queued ATM switch; single iteration scheduling algorithm; single-bit request scheduling algorithm | ||||
| References | ||||
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