DESIGNING AN ARCHITECTURE LEVEL MODEL FOR MULTI-CORE SYSTEMS | ||||
| JES. Journal of Engineering Sciences | ||||
| Article 4, Volume 42, No 6, November and December 2014, Page 1378-1391 PDF (1.02 MB) | ||||
| Document Type: Research Paper | ||||
| DOI: 10.21608/jesaun.2014.115115 | ||||
 View on SCiNiTO | ||||
| Author | ||||
| Hassan Ali Hassan Ahmed Youness | ||||
| Staff in Computers and Systems Eng. Depart, Faculty of Engineering, Minia University, Egypt | ||||
| Abstract | ||||
| The Architecture Level Model (ALM) as a design in space exploration in the early phases of the design process can have a dramatic impact on the area, speed, and power consumption of the resulting systems. A multi-core system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a new approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi- core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and Hardware/Software partition. The back end engine generates a System C simulation model using a well-known commercial tool model generation library to form the architecture level model. The viability and potential of the approach is demonstrated by a case study. | ||||
| Keywords | ||||
| ALM; Multi-core; System C; TPG; MPSoC; TLM | ||||
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