Low Power Current-Mode Threshold Logic Gate Using Nano-Technology Double-Gate MOSFETs | ||||
| The International Conference on Electrical Engineering | ||||
| Article 55, Volume 7, 7th International Conference on Electrical Engineering ICEENG 2010, May 2010, Page 1-10 PDF (251.89 K) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/iceeng.2010.33018 | ||||
 View on SCiNiTO | ||||
| Authors | ||||
| Aliaa Salah Ahmed; Hesham F. A. Hamed; El-sied A. M. Hasaneen | ||||
| Electrical Engineering Depart., Faculty of Engineering. | ||||
| Abstract | ||||
| Abstract: This paper presents a new low voltage low power current mode threshold logic (CMTL) circuits using DGMOSFETs. The ultimate feature of the double gate transistor is using the top and bottom gates in the design of the logic circuits that reduces the number of the transistors. The total number of the transistors required to implement the CMTL circuits and the power dissipation is almost reduced by half by using the DGMOSFET. OR, AND, MAJ logic gates are designed using DGMOSFETs and simulated using HSPICE. The results for the proposed 45 nm DGMOSFET logic circuits with 1 V supply voltage show low power dissipation, smaller power delay product and less number of device. | ||||
| Keywords | ||||
| DGMOSFET Circuits; Low Power Circuits; Threshold Logic Gate | ||||
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