Digital Testing of Analog Circuits | ||||
| Fayoum University Journal of Engineering | ||||
| Volume 7, Issue 2, 2024, Page 45-52 PDF (790.02 K) | ||||
| Document Type: Original Article | ||||
| DOI: 10.21608/fuje.2024.343764 | ||||
 View on SCiNiTO | ||||
| Authors | ||||
Mahmoud A. Moussa  ; Atef L. Salama
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| Giza Engineering Institute, Tammoh | ||||
| Abstract | ||||
| This research exploits digital techniques to test analog circuits. A novel test methodology and an optimization algorithm to generate the stimulus have been developed. The aim is to detect as many manufacturing defects as possible, which might occur during the production process of mixed-signal systems. The test stimulus is a discrete-interval binary sequence identified by the optimiza-tion algorithm. Response from the analog circuit under test (CUT) is digitized with one-bit resolution by a comparator. Digitized responses from the actual circuit and from fault-free simulation are compared for fault recognition. A fig-ure-of-merit, to measure the ability of a specified binary sequence to detect all possible faults, is defined. Input sequences with good performance will generally be too long to permit exhaustive search of all candidates. Instead, iterative op-timization is employed. An optimum sequence has been discovered when no further modification can improve the figure-of-merit. This process of optimiza-tion is performed with computer-based simulation of the circuit under test. Consequently, faults and tolerances can be introduced as required and all as-pects of behavior can be modelled under controlled conditions. The digitized response of the optimum sequence is stored to be used in actual test application. The methodology has been validated using analog filter. All catastrophic and parametric (deviations of component values from nominal by more than six times the normal tolerances) failures can be detected, with detection probability greater than 98%. Benefits of the methodology include ease of introducing bi-nary signals to analog subsystems and reduction of the hardware required for both stimulus generation and response processing. | ||||
| Keywords | ||||
| Analog testing; Analog test stimulus; Binary sequences; Digital testing; Fault detection; Hamming distance; Mixed analog–digital integrated circuits; Optimization of Binary sequences; Testing | ||||
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