A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR
Taha, A., Abo El-Soud, M., Abd-EIGhany, F., Mohamed, H. (1998). A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR. EKB Journal Management System, 1(1st International Conference on Electrical Engineering ICEENG 1998), 69-77. doi: 10.21608/iceeng.1998.60209
A. K. Taha; M. A. Abo El-Soud; F. I. Abd-EIGhany; H. N. Mohamed. "A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR". EKB Journal Management System, 1, 1st International Conference on Electrical Engineering ICEENG 1998, 1998, 69-77. doi: 10.21608/iceeng.1998.60209
Taha, A., Abo El-Soud, M., Abd-EIGhany, F., Mohamed, H. (1998). 'A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR', EKB Journal Management System, 1(1st International Conference on Electrical Engineering ICEENG 1998), pp. 69-77. doi: 10.21608/iceeng.1998.60209
Taha, A., Abo El-Soud, M., Abd-EIGhany, F., Mohamed, H. A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR. EKB Journal Management System, 1998; 1(1st International Conference on Electrical Engineering ICEENG 1998): 69-77. doi: 10.21608/iceeng.1998.60209

A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR

The International Conference on Electrical Engineering
Article 8, Volume 1, 1st International Conference on Electrical Engineering ICEENG 1998, March 1998, Page 69-77  XML PDF (2.14 MB)
Document Type: Original Article
DOI: 10.21608/iceeng.1998.60209
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Authors
A. K. Taha1; M. A. Abo El-Soud2; F. I. Abd-EIGhany3; H. N. Mohamed4
1Ph.D., Head of Dpt. of Electronic Engineering, Military Technical College, Cairo, Egypt.
2Professor, Dpt. of Electronics & Communications, Mansoura University, Mansoura, Egypt.
3Associate professor, Head of Dpt. of Radar and Guidance,Military Technical Collage, Cairo, Egypt.
4Graduate student, Dpt. of Electronic Engineering, Military Technical Collage, Cairo, Egypt.
Abstract
This paper presents a novel design of an FPGA-based, reprogrammable digital clock generator that produces a group of clock signals with variable duty cycles. The realized chip provides up to fourty eight, independent, crystal-controlled, variable-duty-cycle clock outputs; each having a duty-cycle that can be varied from 0.4 % to 99.6 % in 250 steps. The proposed design can be used in a variety of applications. One of the main applications is the adjustment of the synaptic weights of an artificial neural network (ANN). The designed unit can also be used as the basis of a highly flexible pulse generator or a complex waveform generator.
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